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| kinetis km34 sub-family data sheet enabling high accuracy, secure 1-, 2- & 3-phase electricity metering solutions through a powerful analog front end (afe), auto-compensated irtc with hardware tamper detection, segment lcd controller, rich security protection and multiple low power features in a 32-bit arm ? cortex ? -m0+ mcu. this product offers: ? enabling single-chip 1-, 2- & 3-phase metering designs ? afe, security & hmi. single crystal implementation ? single point of calibration during manufacture ? highest accuracy metrology with regional feature support ? multiple ? adcs with pga ? supports neutral disconnect use case ? compliance with welmec/oiml recommendations ? memory & peripheral protection ? hardware tamper detect with time stamping ? low-power rtc, battery backup with tamper memory core ? arm ? cortex ? -m0+ core up to 75 mhz ? metering specific memory mapped arithmetic unit (mmau) clocks ? 75 mhz high-accuracy internal reference clock ? 32 khz, and 4 mhz internal reference clock ? 1 khz lpo clock ? 32.768 khz crystal oscillator in irtc power domain ? 1 mhz to 32 mhz crystal oscillator ? fll and pll system peripherals ? memory protection unit (mpu) ? 4-channel dma controller ? watchdog and ewm ? low-leakage wakeup unit (llwu) ? swd debug interface and micro trace buffer (mtb) ? bit manipulation engine (bme) ? inter-peripheral crossbar switch (xbar) analog modules ? 4 afe channels (4 24-bit ? adcs with pga) ? 16-channel 16-bit sar adc with 4 result registers ? high-speed analog comparator containing a 6-bit dac and programmable reference input ? internal 1.2 v reference voltage 10C15 ppm/ memories ? 256 kb program flash memory ? 32 kb sram operating characteristics ? voltage range: 1.71 to 3.6 v (without afe) ? voltage range: 2.7 to 3.6 v (with afe) ? temperature range (ambient): C40 to 105 c low power features ? 13 power modes to provide power optimization based on application requirements ? 7.69 ma @ 75 mhz run current ? less than 171 a/mhz very low power run current ? 6.05 a very low power stop current ? down to 220 na deep sleep current ? v bat domain current < 1 a with irtc operational ? low-power boot with less than 2.33 ma peak current communication interfaces ? 16-bit spi modules ? low-power uart module ? uart module complying with iso7816-3 ? basic uart module ? i 2 c with smbus MKM34Z256VLL7 mkm34z256vlq7 100 lqfp 14 mm 14 mm pitch 0.5 mm 144 lqfp 20 mm 20 mm pitch 0.5 mm freescale semiconductor, inc. km34p144m75sf0 data sheet: technical data rev. 2, may 2015 ? 2014C2015 freescale semiconductor, inc. all rights reserved.
timers ? quad timer (qtmr) ? periodic interrupt timer (pit) ? low power timer (lptmr) ? programmable delay block (pdb) ? independent real time clock (irtc) human-machine interface ? up to 460 (856, 658) segment lcd controller operating in all low-power modes ? general purpose input/output (gpio) security and integrity modules ? memory mapped cryptographic acceleration unit (mmcau) for aes encryption ? random number generator (rnga), complying with nist: sp800-90 ? programmable cyclic redundancy check (pcrc) ? 80-bit unique identification number per chip the following figure shows the functional modules in the chip. sd adc x4 + pga x4 rtc por osc 32k extal32 pll fll irc 4 mhz irc 32 khz core, system and flash clocks xtal32 xtal extal clk gen llwu pmc digital i/os tamper x4 sd adc channels ips bus ahb crossbar switch cmp x3 afe modulator clock sar adc single ended channels comparator inputs digital i/os digital i/os lcd pins multiple dma requests from modules 4-ch dma egpio (dual port) port p1 s1 s2 s0 mpu aips (ahb to ips) port p0 pit x2 sim lptmr xbar smc vref spi x2 i2c x2 slcd uart x4, dec filter x4 wdog rnga pcrc ewm gpio pins m2 mcg *refer to clocking chapter in reference manual for more detailed diagram on mcg. serial wire debug arm ? cortex ? m0+ core ioport (part of ppb) nvic interrupt from modules serial wire debug m0 fine compensation clock analog front end (afe) accessed by micro transfer buffer (mtb) for trace modules in vdda domain modules in vbat domain modules in vdd domain dma mux tcu mtb (part of ppb) flash controller sram (32 kb) 256 kb flash osc mhz irtc mmau lpuart mmcau bme pdb qtmr figure 1. functional block diagram 2 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. ordering information part number 1 memory adc channels maximum number of gpios flash (kb) sram (kb) MKM34Z256VLL7 256 32 12 72 mkm34z256vlq7 256 32 16 99 1. to confirm current availability of orderable part numbers, go to http://www.freescale.com and perform a part number search. related resources type description resource selector guide the freescale solution advisor is a web-based tool that features interactive application wizards and a dynamic product selector. solution advisor product brief the product brief contains concise overview/summary information to enable quick evaluation of a device for design suitability. km3xpb 1 reference manual the reference manual contains a comprehensive description of the structure and function (operation) of a device. km34p144m75sf0rm 1 data sheet the data sheet includes electrical characteristics and signal connections. this document: km34p144m75sf0 chip errata the chip mask set errata provides additional or corrective information for a particular device mask set. kinetis_m_0n32p 1 package drawing package dimensions are provided in package drawings. 100-lqfp: 98ass23308w 1 144-lqfp: 98ass23177w 1 1. to find the associated resource, go to http://www.freescale.com and perform a search using this term. kinetis km34 sub-family data sheet, rev. 2, may 2015 3 freescale semiconductor, inc. table of contents 1 ratings.................................................................................... 5 1.1 thermal handling ratings................................................. 5 1.2 moisture handling ratings................................................ 5 1.3 esd handling ratings....................................................... 5 1.4 voltage and current operating ratings............................. 6 2 general................................................................................... 6 2.1 ac electrical characteristics............................................. 6 2.2 nonswitching electrical specifications.............................. 6 2.2.1 voltage and current operating requirements....... 6 2.2.2 lvd and por operating requirements................ 7 2.2.3 voltage and current operating behaviors............. 8 2.2.4 power mode transition operating behaviors........ 9 2.2.5 power consumption operating behaviors............ 10 2.2.6 emc radiated emissions operating behaviors..... 12 2.2.7 designing with radiated emissions in mind.......... 12 2.2.8 capacitance attributes......................................... 13 2.3 switching specifications................................................... 13 2.3.1 device clock specifications.................................. 13 2.3.2 general switching specifications......................... 13 2.4 thermal specifications..................................................... 14 2.4.1 thermal operating requirements......................... 14 2.4.2 thermal attributes................................................ 14 3 peripheral operating requirements and behaviors.................. 15 3.1 core modules.................................................................. 15 3.1.1 single wire debug (swd)................................... 16 3.1.2 analog front end (afe)...................................... 16 3.2 clock modules................................................................. 17 3.2.1 mcg specifications.............................................. 17 3.2.2 oscillator electrical specifications........................ 19 3.2.3 32 khz oscillator electrical characteristics........... 22 3.3 memories and memory interfaces................................... 24 3.3.1 flash electrical specifications.............................. 24 3.4 analog............................................................................. 25 3.4.1 adc electrical specifications............................... 25 3.4.2 cmp and 6-bit dac electrical specifications....... 29 3.4.3 voltage reference electrical specifications.......... 31 3.4.4 afe electrical specifications................................ 32 3.5 timers.............................................................................. 36 3.6 communication interfaces............................................... 36 3.6.1 i2c switching specifications................................. 36 3.6.2 uart switching specifications............................ 37 3.6.3 spi switching specifications................................ 37 3.7 human-machine interfaces (hmi).................................... 41 3.7.1 lcd electrical characteristics.............................. 41 4 dimensions............................................................................. 43 4.1 obtaining package dimensions....................................... 43 5 pinout...................................................................................... 43 5.1 km3x_256 signal multiplexing and pin assignments ...... 43 5.2 km3x_256 family pinouts............................................... 48 6 ordering parts......................................................................... 50 6.1 determining valid orderable parts.................................... 50 7 part identification..................................................................... 51 7.1 description....................................................................... 51 7.2 format............................................................................. 51 7.3 fields............................................................................... 51 7.4 example........................................................................... 52 8 terminology and guidelines.................................................... 52 8.1 definition: operating requirement.................................... 52 8.2 definition: operating behavior......................................... 52 8.3 definition: attribute.......................................................... 53 8.4 definition: rating............................................................. 53 8.5 result of exceeding a rating............................................ 54 8.6 relationship between ratings and operating requirements.................................................................... 54 8.7 guidelines for ratings and operating requirements.......... 54 8.8 definition: typical value................................................... 55 8.9 typical value conditions.................................................. 56 9 revision history...................................................................... 56 4 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. 1 ratings 1.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature C55 150 c 1 t sdr solder temperature, lead-free 260 c 2 1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 1.2 moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 3 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 1.3 esd handling ratings symbol description min. max. unit notes v hbm electrostatic discharge voltage, human body model (all pins except reset pin) -4000 +4000 v electrostatic discharge voltage, human body model (reset pin only) -2500 +2500 v 1 v cdm electrostatic discharge voltage, charged-device model (for corner pins) -750 +750 v v cdm electrostatic discharge voltage, charged-device model -500 +500 v 2 v pesd powered esd voltage -6000 +6000 v i lat latch-up current at ambient temperature of 105c -100 +100 ma 1. determined according to jedec standard jesd22-a114, electrostatic discharge (esd) sensitivity testing human body model (hbm) . 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . ratings kinetis km34 sub-family data sheet, rev. 2, may 2015 5 freescale semiconductor, inc. 1.4 voltage and current operating ratings symbol description min. max. unit v dd digital supply voltage C0.3 3.6 v v dio digital input voltage (except reset, extal, and xtal) C0.3 v dd + 0.3 v v dtamper tamper input voltage C0.3 v bat + 0.3 v v aio analog 1 , reset, extal, and xtal input voltage C0.3 v dd + 0.3 v i d instantaneous maximum current single pin limit (applies to all port pins) C25 25 ma v dda analog supply voltage v dd C 0.3 v dd + 0.3 v v bat rtc battery supply voltage C0.3 3.6 v 1. analog pins are defined as pins that do not have an associated general purpose i/o port function. 2 general 2.1 ac electrical characteristics unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. figure 2. input signal measurement reference 2.2 nonswitching electrical specifications general 6 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. 2.2.1 voltage and current operating requirements table 1. voltage and current operating requirements symbol description min. max. unit notes v dd supply voltage when afe is operational 2.7 3.6 v supply voltage when afe is not operational 1.71 3.6 v v dda analog supply voltage 2.7 3.6 v v dd C v dda v dd -to-v dda differential voltage C0.1 0.1 v v ss C v ssa v ss -to-v ssa differential voltage C0.1 0.1 v v bat rtc battery supply voltage 1.71 3.6 v 1 v ih input high voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.7 v dd 0.75 v dd v v v il input low voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.35 v dd 0.3 v dd v v v hys input hysteresis 0.06 v dd v i icdio digital pin negative dc injection current single pin ? v in < v ss C0.3v C5 ma i icaio analog 2 , extal, and xtal pin dc injection current single pin ? v in < v ss C0.3v (negative current injection) ? v in > v dd +0.3v (positive current injection) C3 +3 ma i iccont contiguous pin dc injection current regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins ? negative current injection ? positive current injection C25 +25 ma v rfvbat v bat voltage required to retain the vbat register file v por_vbat v 1. v bat always needs to be there for the chip to be operational. 2. analog pins are defined as pins that do not have an associated general purpose i/o port function. 2.2.2 lvd and por operating requirements table 2. v dd supply lvd and por operating requirements symbol description min. typ. max. unit notes v por falling vdd por detect voltage 0.8 1.1 1.5 v table continues on the next page... general kinetis km34 sub-family data sheet, rev. 2, may 2015 7 freescale semiconductor, inc. table 2. v dd supply lvd and por operating requirements (continued) symbol description min. typ. max. unit notes v lvdh falling low-voltage detect threshold high range (lvdv=01) 2.48 2.56 2.64 v v lvw1h v lvw2h v lvw3h v lvw4h low-voltage warning thresholds high range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 v v v v 1 v hysh low-voltage inhibit reset/recover hysteresis high range 80 mv v lvdl falling low-voltage detect threshold low range (lvdv=00) 1.54 1.60 1.66 v v lvw1l v lvw2l v lvw3l v lvw4l low-voltage warning thresholds low range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 v v v v 1 v hysl low-voltage inhibit reset/recover hysteresis low range 60 mv v bg bandgap voltage reference 0.97 1.00 1.03 v t lpo internal low power oscillator period factory trimmed 900 1000 1100 s 1. rising threshold is the sum of falling threshold and hysteresis voltage table 3. vbat power operating requirements symbol description min. typ. max. unit notes v por_vbat falling vbat supply por detect voltage 0.8 1.1 1.5 v 2.2.3 voltage and current operating behaviors table 4. voltage and current operating behaviors symbol description min. max. unit notes v oh output high voltage low-drive strength ? 2.7 v v dd 3.6 v, i oh = 5 ma ? 1.71 v v dd 2.7 v, i oh = 2.5 ma v dd C 0.5 v dd C 0.5 v v i oht output high current total for all ports 100 ma table continues on the next page... general 8 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. table 4. voltage and current operating behaviors (continued) symbol description min. max. unit notes v ol output low voltage low-drive strength ? 2.7 v v dd 3.6 v, i ol = 5 ma ? 1.71 v v dd 2.7 v, i ol = 2.5 ma 0.5 0.5 v v i olt output low current total for all ports 100 ma i oz hi-z (off-state) leakage current (per pin) 1 a r pu internal pull-up resistors 30 60 k 1 r pd internal pull-down resistors 30 60 k 2 1. measured at v input = v ss . 2. measured at v input = v dd . 2.2.4 power mode transition operating behaviors all specifications except t por , and vllsx run recovery times in the following table assume this clock configuration: ? cpu and system clocks = 75 mhz ? bus clock = 25 mhz ? flash clock = 25 mhz ? temperature: ?40 c, 25 c, and 105 c ? v dd : 1.71 v, 3.3 v, and 3.6 v table 5. power mode transition operating behaviors symbol description min. typ. max. unit notes t por after a por event, amount of time from the point v dd reaches 1.71 v to execute the first instruction across the operating temperature range of the chip. 563 659 s 1 ? vlls0 run 370 382 s ? vlls1 run 370 382 s ? vlls2 run 270 275 s ? vlls3 run 270 275 s ? vlps run 5 6 s ? stop run 5 6 s general kinetis km34 sub-family data sheet, rev. 2, may 2015 9 freescale semiconductor, inc. 1. normal boot (ftfa_opt[lpboot]=1) 2.2.5 power consumption operating behaviors note the maximum (max.) values stated in the following table represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3sigma). table 6. power consumption operating behaviors symbol description min. typ. max. unit notes i dda analog supply current see note ma 1 i dd_run run mode current all peripheral clocks disabled, code executing from flash ? @ 3.0 v ? 25 c ? C40 c ? 105 c 7.69 7.68 7.94 7.954 7.92 8.159 ma ma ma 2 i dd_run run mode current all peripheral clocks enabled, code executing from flash ? @ 3.0 v ? 25 c ? C40 c ? 105 c 12.38 12.32 12.67 12.827 12.758 13.051 ma ma ma 2 i dd_wait wait mode high frequency current at 3.0 v all peripheral clocks disabled and flash is not in low-power ? 25 c ? C40 c ? 105 c 5.48 5.46 5.68 5.612 5.601 5.782 ma ma ma 2 i dd_wait wait mode high frequency current at 3.0 v all peripheral clocks disabled and flash disabled (put in low-power) ? 25 c ? C40 c ? 105 c 4.55 4.56 4.74 4.664 4.683 4.815 ma ma ma 2 , 3 i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks disabled ? 25 c ? C40 c ? 105 c 171 172 280 500 470 900 a a a 4 i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks enabled ? 25 c 341 327 530 500 a a 5 table continues on the next page... general 10 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. table 6. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes ? C40 c ? 105 c 456 1000 a i dd_vlpw very-low-power wait mode current at 3.0 v all peripheral clocks disabled ? 25 c ? C40 c ? 105 c 112 114 226 350 330 800 a a a 6 i dd_stop stop mode current at 3.0 v ? 25 c ? C40 c ? 105 c 404 386 569 730 700 800 a a a i dd_vlps very-low-power stop mode current at 3.0 v ? 25 c ? C40 c ? 105 c 6.05 2.63 145 46 44 700 a a a i dd_vlls3 very low-leakage stop mode 3 current at 3.0 v ? 25 c ? C40 c ? 105 c 2.49 1.97 20.1 3.5 3.3 85 a a a i dd_vlls2 very low-leakage stop mode 2 current at 3.0 v ? 25 c ? C40 c ? 105 c 2.31 1.94 14.5 2.6 2.5 59.5 a a a i dd_vlls1 very low-leakage stop mode 1 current at 3.0 v ? 25 c ? C40 c ? 105 c 1.16 0.937 10.7 1.7 1.6 38.8 a a a i dd_vlls0 very low-leakage stop mode 0 current at 3.0 v with por detect circuit disabled ? 25 c ? C40 c ? 105 c 0.22 0.068 7.72 0.67 0.64 38 a a a i dd_vlls0 very low-leakage stop mode 0 current at 3.0 v with por detect circuit enabled ? 25 c ? C40 c ? 105 c 0.502 0.349 9.07 0.76 0.72 38.4 a a a i dd_vbat average current with rtc and 32 khz disabled at 3.0 v and vdd is off ? 25 c 0.243 0.143 1 0.95 a a table continues on the next page... general kinetis km34 sub-family data sheet, rev. 2, may 2015 11 freescale semiconductor, inc. table 6. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes ? C40 c ? 105 c 6.05 15 a i dd_vbat average current when vdd is off and lfsr and tamper clocks set to 2 hz. ? @ 3.0 v ? 25 c ? C40 c ? 105 c 1.42 1.24 8.04 3 2.5 16 a a a 7 , 8 1. see afe specification for i dda . 2. 75 mhz core and system clock, 25 mhz bus clock, and 25 mhz flash clock. mcg configured for fbe mode. all peripheral clocks disabled. 3. should be reduced by 500 a. 4. 2 mhz core/system clock, and 1 mhz bus/flash clock. mcg configured for blpe mode. all peripheral clocks disabled. code executing while (1) loop from flash. 5. 2 mhz core/system clock, and 1 mhz bus/flash clock. mcg configured for blpe mode. all peripheral clocks enabled but peripherals are not in active operation. code executing while (1) loop from flash. 6. 2 mhz core/system clock, and 1 mhz bus/flash clock. mcg configured for blpe mode. all peripheral clocks disabled. no flash accesses; some activity on dma & ram assumed. 7. includes 32 khz oscillator current and rtc operation. 8. an external power switch for vbat should be present on board to have better battery life and keep vbat pin powered in all conditions. there is no internal power switch in rtc. 2.2.6 emc radiated emissions operating behaviors table 7. emc radiated emissions operating behaviors symbol description frequency band (mhz) typ. unit notes v re1 radiated emissions voltage, band 1 0.15C50 14 dbv v re2 radiated emissions voltage, band 2 50C150 16 dbv v re3 radiated emissions voltage, band 3 150C500 12 dbv v re4 radiated emissions voltage, band 4 500C1000 5 dbv v re_iec iec level 0.15C1000 m 1 1. v dd = 3.3 v, t a = 25 c, f osc = 10 mhz (crystal), f sys = 75 mhz, f bus = 25 mhz 2.2.7 designing with radiated emissions in mind to find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. go to www.freescale.com . 2. perform a keyword search for emc design. general 12 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. 2.2.8 capacitance attributes table 8. capacitance attributes symbol description min. max. unit c in_a input capacitance: analog pins 7 pf c in_d input capacitance: digital pins 7 pf c in_d_io60 input capacitance: fast digital pins 9 pf 2.3 switching specifications 2.3.1 device clock specifications table 9. device clock specifications symbol description min. max. unit notes normal run mode f sys system and core clock 75 mhz f bus bus clock 25 mhz f flash flash clock 25 mhz f afe afe modulator clock 6.5 mhz vlpr mode 1 f sys system and core clock 4 mhz f bus bus clock 1 mhz f flash flash clock 1 mhz f afe afe modulator clock 2 1.6 mhz 1. the frequency limitations in vlpr mode here override any frequency specification listed in the timing specification for any other module. 2. afe working in low-power mode. 2.3.2 general switching specifications these general purpose specifications apply to all signals configured for gpio, uart, and i 2 c signals. general kinetis km34 sub-family data sheet, rev. 2, may 2015 13 freescale semiconductor, inc. table 10. general switching specifications symbol description min. max. unit notes gpio pin interrupt pulse width (digital glitch filter disabled) synchronous path 1.5 bus clock cycles 1 gpio pin interrupt pulse width (digital glitch filter disabled) asynchronous path 16 ns external reset pulse width (digital glitch filter disabled) 100 ns 2 port rise and fall time ? slew disabled ? 1.71 v dd 2.7 v ? 2.7 v dd 3.6 v ? slew enabled ? 1.71 v dd 2.7 v ? 2.7 v dd 3.6 v 8 5 27 16 ns ns ns ns 1. the greater synchronous and asynchronous timing must be met. 2. this is the shortest pulse that is guaranteed to be recognized. 2.4 thermal specifications 2.4.1 thermal operating requirements table 11. thermal operating requirements symbol description min. max. 1 unit t j die junction temperature C40 125 c t a ambient temperature C40 105 c 1. maximum t a can be exceeded only if the user ensures that t j does not exceed maximum t j . the simplest method to determine t j is: t j = t a + r ja chip power dissipation. 2.4.2 thermal attributes board type symbol description 100 lqfp 144 lqfp unit notes single-layer (1s) r ja thermal resistance, junction to ambient 62 55 c/w 1 table continues on the next page... general 14 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. board type symbol description 100 lqfp 144 lqfp unit notes (natural convection) four-layer (2s2p) r ja thermal resistance, junction to ambient (natural convection) 49 46 c/w 1 single-layer (1s) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 52 46 c/w 1 four-layer (2s2p) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 43 40 c/w 1 r jb thermal resistance, junction to board 35 34 c/w 2 r jc thermal resistance, junction to case 18 15 c/w 3 jt thermal characterization parameter, junction to package top outside center (natural convection) 2 2 c/w 4 1. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) , or eia/jedec standard jesd51-6, integrated circuit thermal test method environmental conditionsforced convection (moving air) . 2. determined according to jedec standard jesd51-8, integrated circuit thermal test method environmental conditionsjunction-to-board . 3. determined according to method 1012.1 of mil-std 883, test method standard, microcircuits , with the cold plate temperature used for the case temperature. the value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) . 3 peripheral operating requirements and behaviors peripheral operating requirements and behaviors kinetis km34 sub-family data sheet, rev. 2, may 2015 15 freescale semiconductor, inc. 3.1 core modules 3.1.1 single wire debug (swd) table 12. swd switching characteristics at 2.7 v (2.7-3.6 v) symbol description value unit notes swd clk frequency of swd operation 20 mhz inputs, t sui data setup time 5 ns 1 inputs, t hi data hold time 0 ns 1 after clock edge, t dvo data valid time 32 ns 1 t ho data valid hold 0 ns 1 1. input transition assumed = 1 ns. output transition assumed = 50 pf. table 13. switching characteristics at 1.7 v (1.7-3.6 v) symbol description value unit notes swd clk frequency of swd operation 18 mhz inputs, t sui data setup time 4.7 ns 1 inputs, t hi data hold time 0 ns 1 after clock edge, t dvo data valid time 49.4 ns 2 t ho data valid hold 0 ns 1 1. input transition assumed = 1 ns. output transition assumed = 50 pf. 2. frequency of swd clock (18 mhz) is applicable only in case the input setup time of the device outside is not more than 6.15 ns, else the frequency of swd clock would need to be lowered. 3.1.2 analog front end (afe) afe switching characteristics at (2.7 v-3.6 v) case 1: clock is coming in and data is also coming in (xbar ports timed with respect to afe clock defined at pad ptb7, pte3, and ptk4). table 14. afe switching characteristics (2.7 v-3.6 v) symbol description value unit notes afe clk frequency of operation 10 mhz inputs, t sui data setup time 5 ns 1 inputs, t hi data hold time 0 ns 1 1. input transition: 1 ns. output load: 50 pf. peripheral operating requirements and behaviors 16 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. case 2: clock is going out and data is coming in (xbar ports timed with respect to generated clock defined at the xbar out ports). table 15. afe switching characteristics (2.7 v-3.6 v) symbol description value unit notes afe clk frequency of operation 6.2 mhz inputs, t sui data setup time 36 ns 1 inputs, t hi data hold time 0 ns 1 1. input transition: 1 ns. output load: 50 pf. afe switching characteristics at (1.7 v-3.6 v) case 1: clock is coming in and data is also coming in (xbar ports timed with respect to afe clock defined at pad ptb7, pte3, and ptk4). table 16. afe switching characteristics (1.7 v-3.6 v) symbol description value unit notes afe clk frequency of operation 13 mhz inputs, t sui data setup time 30 ns 1 inputs, t hi data hold time 5 ns 1 1. input transition: 1 ns. output load: 50 pf. case 2: clock is going out and data is coming in (xbar ports timed with respect to generated clock defined at xbar out ports). table 17. afe switching characteristics (1.7 v-3.6 v) symbol description value unit notes afe clk frequency of operation 6.5 mhz inputs, t sui data setup time 36 ns 1 inputs, t hi data hold time 0 ns 1 1. input transition: 1 ns. output load: 50 pf. 3.2 clock modules peripheral operating requirements and behaviors kinetis km34 sub-family data sheet, rev. 2, may 2015 17 freescale semiconductor, inc. 3.2.1 mcg specifications table 18. mcg specifications symbol description min. typ. max. unit notes f ints_ft internal reference frequency (slow clock) factory trimmed at nominal v dd and 25 c 32.768 khz f ints_t total deviation of internal reference frequency (slow clock) over voltage and temperature +0.5/-0.7 % f ints_t total deviation of internal reference frequency (slow clock) over fixed voltage and full operating temperature range -2 +2 % f ints_t internal reference frequency (slow clock) user trimmed 31.25 39.0625 khz fdco_res_t resolution of trimmed average dco output frequency at fixed voltage and temperature using sctrim and scftrim 0.3 0.6 %f dco f dco_t total deviation of trimmed average dco output frequency over voltage and temperature +0.5/-0.7 %f dco 1 f dco_t total deviation of trimmed average dco output frequency over fixed voltage and temperature range of 0C70c 0.4 %f dco 1 f intf_ft internal reference frequency (fast clock) factory trimmed at nominal v dd and 25c 4 mhz f intf_t total deviation of internal reference frequency (fast clock) over voltage and temperature factory trimmed at nominal v dd and 25c +1/-2 % f intf_t internal reference frequency (fast clock) user trimmed at nominal v dd and 25 c 3 5 mhz f loc_low loss of external clock minimum frequency range = 00 (3/5) x f ints_t khz f loc_high loss of external clock minimum frequency range = 01, 10, or 11 (16/5) x f ints_t khz fll f dco dco output frequency range low-range (drs=00) 640 f ints_t 20 20.97 22 mhz 2 , 3 mid-range (drs=01) 1280 f ints_t 40 41.94 45 mhz mid-high range (drs=10) 1920 f ints_t 60 62.91 67 mhz high-range (drs=11) 2560 f ints_t 80 83.89 90 mhz f dco_t_dmx32 dco output frequency low-range (drs=00) 732 f ints_t 23.99 mhz 4 , 5 , 6 table continues on the next page... peripheral operating requirements and behaviors 18 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. table 18. mcg specifications (continued) symbol description min. typ. max. unit notes mid-range (drs=01) 1464 f ints_t 47.97 mhz mid-high range (drs=10) 2197 f ints_t 71.99 mhz high-range (drs=11) 2929 f ints_t 95.98 mhz j cyc_fll fll period jitter 70 140 ps 7 t fll_acquire fll target frequency acquisition time 1 ms 8 pll f vco vco operating frequency 11.71875 12.288 14.6484375 mhz i pll pll operating current ? io 3.3 v current ? max core voltage current 300 100 a f pll_ref pll reference frequency range 31.25 32.768 39.0625 khz j cyc_pll pll period jitter (rms) ? f vco = 12 mhz 700 ps d lock lock entry frequency tolerance 1.49 2.98 % d unl lock exit frequency tolerance 4.47 5.97 % t pll_lock lock detector detection time 150 10 -6 + 1075(1/ f pll_ref ) s 1. this parameter is measured with the internal reference (slow clock) being used as a reference to the fll (fei clock mode). 2. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=0. 3. chip max freq is 75 mhz, so high-range of dco cannot be used and should not be configured. 4. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=1. 5. the resulting clock frequency must not exceed the maximum specified clock frequency of the device. 6. chip max freq is 75 mhz, so high-range of dco cannot be used and should not be configured. 7. this specification is based on standard deviation (rms) of period or frequency. 8. this specification applies to any time the fll reference source or reference divider is changed, trim value is changed, dmx32 bit is changed, drs bits are changed, or changing from fll disabled (blpe, blpi) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 3.2.2 oscillator electrical specifications peripheral operating requirements and behaviors kinetis km34 sub-family data sheet, rev. 2, may 2015 19 freescale semiconductor, inc. 3.2.2.1 oscillator dc electrical specifications table 19. oscillator dc electrical specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i ddosc supply current low-power mode (hgo=0) ? 32 khz ? 1 mhz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz 500 200 200 300 950 1.2 1.5 na a a a a ma ma 1 i ddosc supply current high-gain mode (hgo=1) ? 32 khz ? 1 mhz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz 25 300 400 500 2.5 3 4 a a a a ma ma ma 1 c x extal load capacitance 2 , 3 c y xtal load capacitance 2 , 3 capacitance of extal ? die level (100 lqfp) ? package level (100 lqfp) 247 0.495 ff pf capacitance of xtal ? die level (100 lqfp) ? package level (100 lqfp) 265 0.495 ff pf r f feedback resistor low-frequency, low-power mode (hgo=0) m 2 , 4 feedback resistor low-frequency, high-gain mode (hgo=1) 10 m feedback resistor high-frequency, low-power mode (hgo=0) m feedback resistor high-frequency, high-gain mode (hgo=1) 1 m r s series resistor low-frequency, low-power mode (hgo=0) k series resistor low-frequency, high-gain mode (hgo=1) 200 k table continues on the next page... peripheral operating requirements and behaviors 20 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. table 19. oscillator dc electrical specifications (continued) symbol description min. typ. max. unit notes series resistor high-frequency, low-power mode (hgo=0) k series resistor high-frequency, high-gain mode (hgo=1) ? 1 mhz resonator ? 2 mhz resonator ? 4 mhz resonator ? 8 mhz resonator ? 16 mhz resonator ? 20 mhz resonator ? 32 mhz resonator 6.6 3.3 0 0 0 0 0 k k k k k k k v pp 5 peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode (hgo=1) v dd v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode (hgo=1) v dd v 1. v dd =3.3 v, temperature =25 c 2. see crystal or resonator manufacturer's recommendation 3. c x and c y can be provided by using either integrated capacitors or external components. 4. when low-power mode is selected, r f is integrated and must not be attached externally. 5. the extal and xtal pins should only be connected to required oscillator components and must not be connected to any other device. 3.2.2.2 oscillator frequency specifications table 20. oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency low- frequency mode (mcg_c2[range]=00) 32 40 khz f osc_hi_1 oscillator crystal or resonator frequency high-frequency mode (low range) (mcg_c2[range]=01) 1 8 mhz f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 8 32 mhz table continues on the next page... peripheral operating requirements and behaviors kinetis km34 sub-family data sheet, rev. 2, may 2015 21 freescale semiconductor, inc. table 20. oscillator frequency specifications (continued) symbol description min. typ. max. unit notes f ec_extal input clock frequency (external clock mode) 48 mhz 1 , 2 t dc_extal input clock duty cycle (external clock mode) 40 50 60 % t cst crystal startup time 32 khz low-frequency, low-power mode (hgo=0) ms 3 , 4 crystal startup time 32 khz low-frequency, high-gain mode (hgo=1) ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), low-power mode (hgo=0) 0.6 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), high-gain mode (hgo=1) 1 ms 1. other frequency limits may apply when external clock is being used as a reference for the fll or pll. 2. when transitioning from fei or fbi to fbe mode, restrict the frequency of the input clock so that, when it is divided by frdiv, it remains within the limits of the dco input clock frequency. 3. proper pc board layout procedures must be followed to achieve specifications. 4. crystal startup time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. 3.2.3 32 khz oscillator electrical characteristics 3.2.3.1 32khz oscillator maximum ratings note functional operating conditions are given in dc electrical specifications. absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond those listed may affect device reliability or cause permanent damage to the device. table 21. 32khz oscillator absolute maximum ratings num symbol description min. max. unit 1 v dd33osc rtc oscillator (a_ip_osc_3v32k vlp_nn_c90lp) module 3.3v analog supply voltage C0.3 3.6 v 2 v extal extal input voltage C0.3 3.6 v table continues on the next page... peripheral operating requirements and behaviors 22 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. table 21. 32khz oscillator absolute maximum ratings (continued) num symbol description min. max. unit 3 v xtal xtal input voltage C0.3 3.6 v 4 t a operating temperature range (packaged) C40 135 c 5 t j operating temperature range (junction) C40 135 c 6 t stg storage temperature range C65 150 c 3.2.3.2 32 khz oscillator dc electrical specifications table 22. 32khz oscillator dc electrical specifications symbol description min. typ. max. unit v bat supply voltage 1.71 3.6 v r f internal feedback resistor 100 m c para parasitical capacitance of extal32 and xtal32 5 7 pf v pp 1 peak-to-peak amplitude of oscillation 0.6 v 1. when a crystal is being used with the 32 khz oscillator, the extal32 and xtal32 pins should only be connected to required oscillator components and must not be connected to any other devices. 3.2.3.3 32 khz oscillator frequency specifications table 23. 32 khz oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal 32.768 khz t start crystal start-up time 1000 ms 1 f ec_extal32 externally provided input clock frequency 32.768 khz 2 v ec_extal32 externally provided input clock amplitude 700 v bat mv 2 , 3 1. proper pc board layout procedures must be followed to achieve specifications. 2. this specification is for an externally supplied clock driven to extal32 and does not apply to any other clock input. the oscillator remains enabled and xtal32 must be left unconnected. 3. the parameter specified is a peak-to-peak value and v ih and v il specifications do not apply. the voltage of the applied clock must be within the range of v ss to v bat . note the 32 khz oscillator works in low power mode by default and cannot be moved into high power/gain mode. peripheral operating requirements and behaviors kinetis km34 sub-family data sheet, rev. 2, may 2015 23 freescale semiconductor, inc. 3.3 memories and memory interfaces 3.3.1 flash electrical specifications this section describes the electrical characteristics of the flash memory module. 3.3.1.1 flash timing specifications program and erase the following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. table 24. nvm program/erase timing specifications symbol description min. typ. max. unit notes t hvpgm4 longword program high-voltage time 7.5 18 s t hversscr sector erase high-voltage time 13 113 ms 1 t hversall erase all high-voltage time 52 452 ms 1 1. maximum time based on expectations at cycling end-of-life. 3.3.1.2 flash timing specifications commands table 25. flash command timing specifications symbol description min. typ. max. unit notes t rd1sec1k read 1s section execution time (flash sector) 60 s 1 t pgmchk program check execution time 45 s 1 t rdrsrc read resource execution time 30 s 1 t pgm4 program longword execution time 65 145 s t ersscr erase flash sector execution time 14 114 ms 2 t rd1all read 1s all blocks execution time 1.8 ms 1 t rdonce read once execution time 25 s 1 t pgmonce program once execution time 65 s t ersall erase all blocks execution time 88 650 ms 2 t vfykey verify backdoor access key execution time 30 s 1 1. assumes 25 mhz flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. peripheral operating requirements and behaviors 24 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. 3.3.1.3 flash high voltage current behaviors table 26. flash high voltage current behaviors symbol description min. typ. max. unit i dd_pgm average current adder during high voltage flash programming operation 2.5 6.0 ma i dd_ers average current adder during high voltage flash erase operation 1.5 4.0 ma 3.3.1.4 reliability specifications table 27. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 50 years t nvmretp1k data retention after up to 1 k cycles 20 100 years n nvmcycp cycling endurance 10 k 50 k cycles 2 1. typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 c use profile. engineering bulletin eb618 does not apply to this technology. typical endurance defined in engineering bulletin eb619. 2. cycling endurance represents number of program/erase cycles at C40 c t j 105 c. 3.4 analog 3.4.1 adc electrical specifications all adc channels meet the 12-bit single-ended accuracy specifications. 3.4.1.1 16-bit adc operating conditions table 28. 16-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v dda supply voltage delta to v dd (v dd C v dda ) -100 0 +100 mv 2 v ssa ground voltage delta to v ss (v ss C v ssa ) -100 0 +100 mv 2 v refh adc reference voltage high absolute v dda v dda v dda v 3 v refl adc reference voltage low absolute v ssa v ssa v ssa v 4 table continues on the next page... peripheral operating requirements and behaviors kinetis km34 sub-family data sheet, rev. 2, may 2015 25 freescale semiconductor, inc. table 28. 16-bit adc operating conditions (continued) symbol description conditions min. typ. 1 max. unit notes v adin input voltage v ssa v dda v c adin input capacitance ? 16-bit mode ? 8-bit / 10-bit / 12-bit modes 8 4 10 5 pf r adin input series resistance 2 5 k r as analog source resistance (external) 12-bit modes f adck < 4 mhz 5 k 5 f adck adc conversion clock frequency 12-bit mode 1.0 18.0 mhz 6 f adck adc conversion clock frequency 16-bit mode 2.0 12.0 mhz 6 c rate adc conversion rate 12-bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 20.000 818.330 ksps 7 c rate adc conversion rate 16-bit mode no adc hardware averaging continuous conversions enabled, subsequent conversion time 37.037 461.467 ksps 7 1. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 1.0 mhz, unless otherwise stated. typical values are for reference only, and are not tested in production. 2. dc potential difference. 3. v refh is internally tied to v dda . 4. v refl is internally tied to v ssa . 5. this resistance is external to mcu. to achieve the best results, the analog source resistance must be kept as low as possible. the results in this data sheet were derived from a system that had < 8 analog source resistance. the r as /c as time constant should be kept to < 1 ns. 6. to use the maximum adc conversion clock frequency, cfg2[adhsc] must be set and cfg1[adlpc] must be clear. 7. for guidelines and examples of conversion rate calculation, download the adc calculator tool . peripheral operating requirements and behaviors 26 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. r as v as c as z as v adin z adin r adin r adin r adin r adin c adin pad leakage due to input protection input pin input pin input pin simplified input pin equivalent circuit simplified channel select circuit adc sar engine figure 3. adc input impedance equivalency diagram 3.4.1.2 16-bit adc electrical characteristics table 29. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) symbol description conditions 1 min. typ. 2 max. unit notes i dda_adc supply current 0.215 1.7 ma 3 f adack adc asynchronous clock source ? adlpc = 1, adhsc = 0 ? adlpc = 1, adhsc = 1 ? adlpc = 0, adhsc = 0 ? adlpc = 0, adhsc = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 mhz mhz mhz mhz t adack = 1/f adack sample time see reference manual chapter for sample times tue total unadjusted error ? 12-bit modes ? <12-bit modes 4 1.4 6.8 2.1 lsb 4 5 dnl differential non- linearity ? 12-bit modes ? <12-bit modes 0.7 0.2 C1.1 to +1.9 C0.3 to +0.5 lsb 4 5 inl integral non- linearity ? 12-bit modes 1.0 0.5 C2.7 to +1.9 lsb 4 5 table continues on the next page... peripheral operating requirements and behaviors kinetis km34 sub-family data sheet, rev. 2, may 2015 27 freescale semiconductor, inc. table 29. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes ? <12-bit modes C0.7 to +0.5 e fs full-scale error ? 12-bit modes ? <12-bit modes C4 C1.4 C5.4 C1.8 lsb 4 v adin = v dda 5 e q quantization error ? 16-bit modes ? 12-bit modes C1 to 0 0.5 lsb 4 enob effective number of bits 16-bit single-ended mode ? avg = 32 ? avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits 6 sinad signal-to-noise plus distortion see enob 6.02 enob + 1.76 db thd total harmonic distortion 16-bit single-ended mode ? avg = 32 -94 -85 db db 7 sfdr spurious free dynamic range 16-bit single-ended mode ? avg = 32 82 78 95 90 db db 7 e il input leakage error i in r as mv i in = leakage current (refer to the mcu's voltage and current operating ratings) temp sensor slope across the full temperature range of the device 1.55 1.62 1.69 mv/c 8 v temp25 temp sensor voltage 25 c 706 716 726 mv 8 1. all accuracy numbers assume the adc is calibrated with v refh = v dda 2. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. peripheral operating requirements and behaviors 28 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. 3. the adc supply current depends on the adc conversion clock speed, conversion rate and adc_cfg1[adlpc] (low power). for lowest power operation, adc_cfg1[adlpc] must be set, the adc_cfg2[adhsc] bit must be clear with 1 mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n 5. adc conversion clock < 16 mhz, max hardware averaging (avge = %1, avgs = %11) 6. input data is 100 hz sine wave. adc conversion clock < 12 mhz. 7. input data is 1 khz sine wave. adc conversion clock < 12 mhz. 8. adc conversion clock < 3 mhz typical adc 16-bit single-ended enob vs adc clock 100hz, 90% fs sine input enob adc clock frequency (mhz) 14.00 13.75 13.25 13.00 12.75 12.50 12.00 11.75 11.50 11.25 11.00 1 2 3 4 5 6 7 8 9 10 1211 averaging of 4 samples averaging of 32 samples 13.50 12.25 figure 4. typical enob vs. adc_clk for 16-bit single-ended mode 3.4.2 cmp and 6-bit dac electrical specifications table 30. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 1.71 3.6 v i ddhs supply current, high-speed mode (en=1, pmode=1) 200 a i ddls supply current, low-speed mode (en=1, pmode=0) 20 a v ain analog input voltage v ss C 0.3 v dd v v aio analog input offset voltage 20 mv v h analog comparator hysteresis 1 ? cr0[hystctr] = 00 ? cr0[hystctr] = 01 ? cr0[hystctr] = 10 ? cr0[hystctr] = 11 5 10 20 30 mv mv mv mv v cmpoh output high v dd C 0.5 v table continues on the next page... peripheral operating requirements and behaviors kinetis km34 sub-family data sheet, rev. 2, may 2015 29 freescale semiconductor, inc. table 30. comparator and 6-bit dac electrical specifications (continued) symbol description min. typ. max. unit v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en=1, pmode=1) 20 50 200 ns t dls propagation delay, low-speed mode (en=1, pmode=0) 80 250 600 ns analog comparator initialization delay 2 40 s i dac6b 6-bit dac current adder (enabled) 7 a inl 6-bit dac integral non-linearity C0.5 0.5 lsb 3 dnl 6-bit dac differential non-linearity C0.3 0.3 lsb 1. typical hysteresis is measured with input voltage range limited to 0.6 to v dd C0.6 v. 2. comparator initialization delay is defined as the time between software writes to change control inputs (writes to cmp_daccr[dacen], cmp_daccr[vrsel], cmp_daccr[vosel], cmp_muxcr[psel], and cmp_muxcr[msel]) and the comparator output settling to a stable level. 3. 1 lsb = v reference /64 00 01 10 hystctr setting 0.1 10 11 vin level (v) cmp hystereris (v) 3.1 2.82.5 2.2 1.91.61.3 1 0.70.4 0.05 0 0.01 0.02 0.03 0.08 0.07 0.06 0.04 figure 5. typical hysteresis vs. vin level (vdd = 3.3 v, pmode = 0) peripheral operating requirements and behaviors 30 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. 00 01 10 hystctr setting 10 11 0.1 3.12.82.5 2.2 1.91.61.3 1 0.70.4 0.1 0 0.02 0.04 0.06 0.18 0.14 0.12 0.08 0.16 vin level (v) cmp hysteresis (v) figure 6. typical hysteresis vs. vin level (vdd = 3.3 v, pmode = 1) 3.4.3 voltage reference electrical specifications table 31. 1.2 vref full-range operating requirements symbol description min. max. unit notes v dda supply voltage 2.7 1 3.6 v t a temperature ?40 105 c c l output load capacitance 100 nf 2 , 3 1. afe is enabled. 2. c l must be connected between vrefh and vrefl. 3. the load capacitance should not exceed 25% of the nominal specified c l value over the operating temperature range of the device. table 32. vref full-range operating behaviors symbol description min. typ. max. unit notes vrefh voltage reference output with factory trim at nominal v dda and temperature = 25 c 1.1915 1.195 1.2027 v table continues on the next page... peripheral operating requirements and behaviors kinetis km34 sub-family data sheet, rev. 2, may 2015 31 freescale semiconductor, inc. table 32. vref full-range operating behaviors (continued) symbol description min. typ. max. unit notes vrefh voltage reference output with factory trim 1.1584 1.2376 v vrefh voltage reference output user trim 1.178 1.202 v vrefl voltage reference output 0.38 0.4 0.42 v v step voltage reference trim step 0.5 mv v tdrift temperature drift when icomp = 0 across full temperature range 18 ppm/oc temperature drift when icomp = 1 across full temperature range 6 ppm/c 1 temperature drift when icomp = 1 across -40 oc to 70 oc 5 ppm/c 1 , 2 temperature drift when icomp = 1 across 0 oc to 50 oc 3 ppm/c 1 , 2 ac aging coefficient 400 uv/yr i bg bandgap only current 80 a 2 i lp low-power buffer current 0.19 ma 2 i hp high-power buffer current 0.5 ma 2 i load vref buffer current C2 2 ma 3 , 4 v load load regulation ? current = 1.0 ma 200 v 2 , 5 t stup buffer startup time 20 ms v vdrift voltage drift (vrefhmax -vrefhmin across the full voltage range) 0.5 mv 2 1. icomp=1 is recommended to get best temperature drift. chopen bit = 1 is also recommended. 2. see the chip's reference manual for the appropriate settings of vref status and control register. 3. 2 ma i load is only achievable for above 2.7 v v dda condition. 4. see the chip's reference manual for the appropriate settings of sim miscellaneous control register. 5. load regulation voltage is the difference between vrefh voltage with no load vs. voltage with defined load. note temperature drift per degree is ( (vrefhmax-vrefhmin)/ (temperature range)/vrefhmin ) in ppm/oc 3.4.4 afe electrical specifications peripheral operating requirements and behaviors 32 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. 3.4.4.1 ? adc + pga specifications table 33. ? adc + pga specifications symbo l description conditions min typ 1 max unit notes f nyq input bandwidth normal mode low-power mode 1.5 1.5 1.5 1.5 1.5 1.5 khz v cm input common mode reference 0 0.8 v vin diff differential input range gain = 1 (pga on/off) 2 500 mv gain = 2 250 mv gain = 4 125 mv gain = 8 62 mv gain = 16 31 mv gain = 32 15 mv snr signal to noise ratio normal mode ? f in =50 hz; gain=01, common mode=0v, v pp =1000mv (full range diff.) ? f in =50 hz; gain=02, common mode=0v, v pp = 500mv (differential ended) ? f in =50 hz; gain=04, common mode=0v, v pp = 250mv (differential ended) ? f in =50 hz; gain=08, common mode=0v, v pp = 125mv (differential ended) ? f in =50 hz; gain=16, common mode=0v, v pp = 62mv (differential ended) ? f in =50 hz; gain=32, common mode=0v, v pp = 31mv (differential ended) 90 88 82 76 70 64 92 90 86 82 78 74 db low-power mode ? f in =50 hz; gain=01, common mode=0v, v pp =1000mv (full range diff.) ? f in =50 hz; gain=02, common mode=0v, v pp = 500mv (differential ended) ? f in =50 hz; gain=04, common mode=0v, v pp = 250mv (differential ended ) ? f in =50 hz; gain=08, common mode=0v, v pp = 125mv (differential ended ) 82 76 70 64 58 82 78 74 70 66 db table continues on the next page... peripheral operating requirements and behaviors kinetis km34 sub-family data sheet, rev. 2, may 2015 33 freescale semiconductor, inc. table 33. ? adc + pga specifications (continued) symbo l description conditions min typ 1 max unit notes ? f in =50 hz; gain=16, common mode=0v, v pp = 62mv (differential ended ) ? f in =50 hz; gain=32, common mode=0v, v pp = 31mv (differential ended ) 52 62 sinad signal-to-noise + distortion ratio normal mode ? f in =50 hz; gain=01, common mode=0v, v pp =500mv (differential ended ) 78 db low-power mode ? f in =50 hz; gain=01, common mode=0v, v pp =500mv (differential ended ) 74 db cmmr common mode rejection ratio ? f in =50 hz; gain=01, common mode=0v, vid=100 mv ? f in =50 hz; gain=32, common mode=0v, v id =100 mv 70 70 db e offset offset error gain=01, v pp =1000 mv (full range diff.) 5 mv offset te mp offset temperature drift 3 gain=01, v pp =1000 mv (full range diff.) 25 ppm/ gain tem p gain temperature drift - gain error caused by temperature drifts 4 ? gain=01, v pp =500 mv (differential ended) ? gain=32, v pp =15 mv (differential ended) 75 ppm/ psrr a c ac power supply rejection ratio gain=01, vcc = 3 v 100 mv, f in = 50 hz 60 db xt crosstalk (with the input of the affected channel grounded) gain=01, v id = 500 mv, f in = 50 hz -100 db f mclk modulator clock frequency range normal mode low-power mode 0.03 0.03 6.5 1.6 mhz i dda_pg a current consumption by pga (each channel) normal mode (f mclk = 6.144 mhz, osr= 2048) low-power mode (f mclk = 0.768 mhz, osr= 256) 2.6 0 ma 5 i dda_ad c current consumption by adc (each channel) normal mode (f mclk = 6.144 mhz, osr= 2048) low-power mode (f mclk = 0.768 mhz, osr= 256) 1.4 0.5 ma 1. typical values assume v dda = 3.0 v, temp = 25c, f mclk = 6.144 mhz, osr = 2048 for normal mode and f mclk = 768 khz, osr = 256 for low-power mode unless otherwise stated. typical values are for reference only and are not tested in production. 2. the full-scale input range in single-ended mode is 0.5v pp . peripheral operating requirements and behaviors 34 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. 3. represents combined offset temperature drift of the pga, sd adc and internal 1.2 vref blocks; defined by shorting both differential inputs to ground. 4. represents combined gain temperature drift of the pga, sd adc and internal 1.2 vref blocks. 5. pga is disabled in low-power modes. 3.4.4.2 ? adc standalone specifications table 34. ? adc standalone specifications symbo l description conditions min typ 1 max unit notes f nyq input bandwidth normal mode low-power mode 1.5 1.5 1.5 1.5 1.5 1.5 khz v cm input common mode reference 0 0.8 v vin diff input range differential 500 mv single ended 250 mv snr signal to noise ratio normal mode ? f in =50 hz; common mode=0 v, v pp = 500 mv (differential ended ) ? f in =50 hz; common mode=0 v, v pp = 500 mv (full range se.) low-power mode ? f in =50 hz; common mode=0 v, v pp =500 mv (diff.) ? f in =50 hz; common mode=0 v, v pp =500 mv (full range se.) 88 76 90 78 db gain tem p gain temperate drift - gain error caused by temperature drifts 2 ? gain bypassed v pp = 500 mv (differential) ? pga bypassed v pp = 500 mv (differential), v cm = 0 v 55 ppm/ offset te mp offset temperate drift - offset error caused by temperature drifts 3 ? gain bypassed vpp = 500 mv (differential), v cm = 0 v 30 ppm/ sinad signal-to-noise + distortion ratio normal mode ? f in =50 hz; common mode=0 v, v pp = 500 mv (diff.) ? f in =50 hz; common mode=0 v, v pp = 500 mv (full range se.) low-power mode ? f in =50 hz; common mode=0 v, v pp =500 mv (diff.) ? f in =50 hz; common mode=0 v, v pp =500 mv (full range se.) 80 74 db cmmr common mode rejection ratio ? f in =50 hz; common mode=0 v, v id =100 mv 90 db table continues on the next page... peripheral operating requirements and behaviors kinetis km34 sub-family data sheet, rev. 2, may 2015 35 freescale semiconductor, inc. table 34. ? adc standalone specifications (continued) symbo l description conditions min typ 1 max unit notes psrr a c ac power supply rejection ratio gain=01, vcc = 3 v 100 mv, f in = 50 hz 60 db xt crosstalk gain=01, v id = 500 mv, f in = 50 hz -100 db f mclk modulator clock frequency range normal mode low-power mode 0.03 0.03 6.5 1.6 mhz i dda_ad c current consumption by adc (each channel) normal mode (f mclk = 6.144 mhz, osr= 2048) low-power mode (f mclk = 0.768 mhz, osr= 256) 1.4 0.5 ma 1. typical values assume v dda = 3.0 v, temp = 25c, f mclk = 6.144 mhz, osr = 2048 for normal mode and f mclk = 768 khz, osr = 256 for low-power mode unless otherwise stated. typical values are for reference only and are not tested in production. 2. represent combined gain temperature drift of the sd adc, and internal 1.2 vref blocks. 3. represent combined offset temperature drift of the sd adc, and internal 1.2 vref blocks; defined by shorting both differential inputs to ground. 3.4.4.3 external modulator interface the external modulator interface on this device comprises of a clock signal and 1-bit data signal. depending on the modulator device being used the interface works as follows: ? clock supplied to external modulator which drives data on rising edge and the km device captures it on falling edge or next rising edge. ? clock and data are supplied by external modulator and km device can sample it on falling edge or next rising edge. depending on control bit in afe, the sampling edge is changed. 3.5 timers see general switching specifications . 3.6 communication interfaces 3.6.1 i2c switching specifications see general switching specifications . peripheral operating requirements and behaviors 36 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. 3.6.2 uart switching specifications see general switching specifications . 3.6.3 spi switching specifications the serial peripheral interface (spi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the following tables provide timing characteristics for classic spi timing modes. see the spi chapter of the chip's reference manual for information about the modified transfer formats used for communicating with slower peripheral devices. all timing is shown with respect to 20% v dd and 80% v dd thresholds, unless noted, as well as input signal transitions of 3 ns and a 30 pf maximum load on all spi pins. table 35. spi master mode timing on slew rate disabled pads num. symbol description min. max. unit note 1 f op frequency of operation f periph /2048 f periph /2 hz 1 2 t spsck spsck period 2 x t periph 2048 x t periph ns 2 3 t lead enable lead time 1/2 t spsck 4 t lag enable lag time 1/2 t spsck 5 t wspsck clock (spsck) high or low time t periph - 30 1024 x t periph ns 6 t su data setup time (inputs) 18 ns 7 t hi data hold time (inputs) 0 ns 8 t v data valid (after spsck edge) 15 ns 9 t ho data hold time (outputs) 0 ns 10 t ri rise time input t periph - 25 ns t fi fall time input 11 t ro rise time output 25 ns t fo fall time output 1. for both spi0 and spi1, f periph is the system clock (f sys ). 2. t periph = 1/f periph table 36. spi master mode timing on slew rate enabled pads num. symbol description min. max. unit note 1 f op frequency of operation f periph /2048 f periph /2 hz 1 table continues on the next page... peripheral operating requirements and behaviors kinetis km34 sub-family data sheet, rev. 2, may 2015 37 freescale semiconductor, inc. table 36. spi master mode timing on slew rate enabled pads (continued) num. symbol description min. max. unit note 2 t spsck spsck period 2 x t periph 2048 x t periph ns 2 3 t lead enable lead time 1/2 t spsck 4 t lag enable lag time 1/2 t spsck 5 t wspsck clock (spsck) high or low time t periph - 30 1024 x t periph ns 6 t su data setup time (inputs) 96 ns 7 t hi data hold time (inputs) 0 ns 8 t v data valid (after spsck edge) 52 ns 9 t ho data hold time (outputs) 0 ns 10 t ri rise time input t periph - 25 ns t fi fall time input 11 t ro rise time output 36 ns t fo fall time output 1. for both spi0 and spi1, f periph is the system clock (f sys ). 2. t periph = 1/f periph (output) 2 8 6 7 msb in 2 lsb in msb out 2 lsb out 9 5 5 3 (cpol=0) 4 11 11 10 10 spsck spsck (cpol=1) 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 1. if configured as an output. ss 1 (output) (output) mosi (output) miso (input) bit 6 . . . 1 bit 6 . . . 1 figure 7. spi master mode timing (cpha = 0) peripheral operating requirements and behaviors 38 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. < table 38. spi slave mode timing on slew rate enabled pads num. symbol description min. max. unit note 1 f op frequency of operation 0 f periph /4 hz 1 2 t spsck spsck period 4 x t periph ns 2 3 t lead enable lead time 1 t periph 4 t lag enable lag time 1 t periph 5 t wspsck clock (spsck) high or low time t periph - 30 ns 6 t su data setup time (inputs) 2 ns 7 t hi data hold time (inputs) 7 ns 8 t a slave access time t periph ns 3 9 t dis slave miso disable time t periph ns 4 10 t v data valid (after spsck edge) 122 ns 11 t ho data hold time (outputs) 0 ns 12 t ri rise time input t periph - 25 ns t fi fall time input 13 t ro rise time output 36 ns t fo fall time output 1. for both spi0 and spi1, f periph is the system clock (f sys ). 2. t periph = 1/f periph 3. time to data active from high-impedance state 4. hold time to high-impedance state 2 10 6 7 msb in bit 6 . . . 1 slave msb slave lsb out 11 5 5 3 8 4 13 note: not defined 12 12 11 see note 13 9 see note (input) (cpol=0) spsck spsck (cpol=1) ss (input) (input) mosi (input) miso (output) lsb in bit 6 . . . 1 figure 9. spi slave mode timing (cpha = 0) peripheral operating requirements and behaviors 40 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. 2 6 7 msb in bit 6 . . . 1 msb out slave lsb out 5 5 10 12 13 3 12 13 4 slave 8 9 see note (input) (cpol=0) spsck spsck (cpol=1) ss (input) (input) mosi (input) miso (output) note: not defined 11 lsb in bit 6 . . . 1 figure 10. spi slave mode timing (cpha = 1) 3.7 human-machine interfaces (hmi) 3.7.1 lcd electrical characteristics table 39. lcd electricals symbol description min. typ. max. unit notes f frame lcd frame frequency ? gcr[ffr]=0 ? gcr[ffr]=1 23.3 46.6 73.1 146.2 hz hz c lcd lcd charge pump capacitance nominal value 100 nf c bylcd lcd bypass capacitance nominal value 100 nf 1 c glass lcd glass capacitance 2000 8000 pf 2 v ireg v ireg ? rvtrim=0000 ? rvtrim=1000 ? rvtrim=0100 ? rvtrim=1100 ? rvtrim=0010 ? rvtrim=1010 ? rvtrim=0110 0.91 0.92 0.93 0.94 0.96 0.97 0.98 v 3 table continues on the next page... peripheral operating requirements and behaviors kinetis km34 sub-family data sheet, rev. 2, may 2015 41 freescale semiconductor, inc. table 39. lcd electricals (continued) symbol description min. typ. max. unit notes ? rvtrim=1110 ? rvtrim=0001 ? rvtrim=1001 ? rvtrim=0101 ? rvtrim=1101 ? rvtrim=0011 ? rvtrim=1011 ? rvtrim=0111 ? rvtrim=1111 0.99 1.01 1.02 1.03 1.05 1.06 1.07 1.08 1.09 rtrim v ireg trim resolution 3.0 % v ireg i vireg v ireg current adder rven = 1 1 a i rbias rbias current adder ? ladj = 10 or 11 high load (lcd glass capacitance 8000 pf) ? ladj = 00 or 01 low load (lcd glass capacitance 2000 pf) 10 1 a a r rbias rbias resistor values ? ladj = 10 or 11 high load (lcd glass capacitance 8000 pf) ? ladj = 00 or 01 low load (lcd glass capacitance 2000 pf) 0.28 2.98 m m vll1 vll1 voltage v ireg v 4 vll2 vll2 voltage 2 x v ireg v 4 vll3 vll3 voltage 3 x v ireg v 4 vll1 vll1 voltage v dda / 3 v 5 vll2 vll2 voltage v dda / 1.5 v 5 vll3 vll3 voltage v dda v 5 1. the actual value used could vary with tolerance. 2. for highest glass capacitance values, lcd_gcr[ladj] should be configured as specified in the lcd controller chapter within the device's reference manual. 3. v ireg maximum should never be externally driven to any level other than v dd - 0.15 v 4. vll1, vll2 and vll3 are a function of v ireg only when the regulator is enabled (gcr[rven]=1) and the charge pump is enabled (gcr[cpsel]=1). 5. vll1, vll2 and vll3 are a function of v dda only under either of the following conditions: ? the charge pump is enabled (gcr[cpsel]=1), the regulator is disabled (gcr[rven]=0), and vll3 = v dda through the internal power switch (gcr[vsupply]=0). ? the resistor bias string is enabled (gcr[cpsel]=0), the regulator is disabled (gcr[rven]=0), and vll3 is connected to v dda externally (gcr[vsupply]=1). peripheral operating requirements and behaviors 42 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. 4 dimensions 4.1 obtaining package dimensions package dimensions are provided in package drawings. to find a package drawing, go to freescale.com and perform a keyword search for the drawings document number: if you want the drawing for this package then use this document number 100-pin lqfp 98ass23308w 144-pin lqfp 98ass23177w 5 pinout 5.1 km3x_256 signal multiplexing and pin assignments 144 qfp 100 qfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 1 nc nc 2 nc nc 3 pti5 disabled lcd_p45 pti5 lcd_p45 4 1 pta0/ llwu_p16 disabled lcd_p23 pta0/ llwu_p16 lcd_p23 5 2 pta1 disabled lcd_p24 pta1 lcd_p24 6 pti6 disabled lcd_p46 pti6 uart2_rx lcd_p46 7 pti7 disabled lcd_p47 pti7 uart2_tx lcd_p47 8 3 pta2 disabled lcd_p25 pta2 lcd_p25 9 4 pta3 disabled lcd_p26 pta3 lcd_p26 10 5 pta4/ llwu_p15 nmi_b lcd_p27 pta4/ llwu_p15 lcd_p27 nmi_b 11 6 pta5 disabled lcd_p28 pta5 cmp0_out lcd_p28 12 7 pta6/ llwu_p14 disabled lcd_p29 pta6/ llwu_p14 xbar_in0 lcd_p29 13 8 pta7 disabled lcd_p30 pta7 xbar_out0 lcd_p30 14 ptj0 disabled lcd_p48 ptj0 i2c1_sda lcd_p48 15 ptj1 disabled lcd_p49 ptj1 i2c1_scl lcd_p49 dimensions kinetis km34 sub-family data sheet, rev. 2, may 2015 43 freescale semiconductor, inc. 144 qfp 100 qfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 16 9 ptb0 disabled lcd_p31 ptb0 lcd_p31 17 ptj2 disabled lcd_p50 ptj2 lcd_p50 18 10 vdd vdd vdd 19 11 vss vss vss 20 12 ptb1/ llwu_p17 disabled lcd_p32 ptb1/ llwu_p17 lcd_p32 21 13 ptb2 disabled lcd_p33 ptb2 lcd_p33 22 14 ptb3 disabled lcd_p34 ptb3 lcd_p34 23 15 ptb4 disabled lcd_p35 ptb4 lcd_p35 24 16 ptb5 disabled lcd_p36 ptb5 lcd_p36 25 17 ptb6 disabled lcd_p37/ cmp1_in0 ptb6 lcd_p37 26 18 ptb7 disabled lcd_p38 ptb7 afe_clk lcd_p38 27 19 ptc0 disabled lcd_p39 ptc0 uart3_rts_ b xbar_in1 pdb0_extrg lcd_p39 28 20 ptc1 disabled lcd_p40/ cmp1_in1 ptc1 uart3_cts_ b lcd_p40 29 21 ptc2 disabled lcd_p41 ptc2 uart3_tx xbar_out1 lcd_p41 30 22 ptc3/ llwu_p13 disabled lcd_p42/ cmp0_in3 ptc3/ llwu_p13 uart3_rx lcd_p42 31 23 ptc4 disabled lcd_p43 ptc4 lcd_p43 32 24 vbat vbat vbat 33 25 xtal32 xtal32 xtal32 34 26 extal32 extal32 extal32 35 nc nc 36 nc nc 37 nc nc 38 nc nc 39 27 vss vss vss 40 28 tamper2 tamper2 tamper2 41 29 tamper1 tamper1 tamper1 42 30 tamper0 tamper0 tamper0 43 31 afe_vdda afe_vdda afe_vdda 44 32 afe_vssa afe_vssa afe_vssa 45 33 afe_sdadp0 afe_sdadp0 afe_sdadp0 46 34 afe_sdadm0 afe_sdadm0 afe_sdadm0 47 35 afe_sdadp1 afe_sdadp1 afe_sdadp1 48 36 afe_sdadm1 afe_sdadm1 afe_sdadm1 49 37 vrefh vrefh vrefh 50 38 vrefl vrefl vrefl pinout 44 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. 144 qfp 100 qfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 51 39 afe_ sdadp2/ cmp1_in2 afe_ sdadp2/ cmp1_in2 afe_ sdadp2/ cmp1_in2 52 40 afe_ sdadm2/ cmp1_in3 afe_ sdadm2/ cmp1_in3 afe_ sdadm2/ cmp1_in3 53 41 vref vref vref 54 42 afe_ sdadp3/ cmp1_in4 afe_ sdadp3/ cmp1_in4 afe_ sdadp3/ cmp1_in4 55 43 afe_ sdadm3/ cmp1_in5 afe_ sdadm3/ cmp1_in5 afe_ sdadm3/ cmp1_in5 56 nc nc 57 nc nc 58 44 ptc5/ llwu_p12 disabled adc0_se0/ cmp2_in0 ptc5/ llwu_p12 uart0_rts_ b 59 45 ptc6 disabled adc0_se1/ cmp2_in1 ptc6 uart0_cts_ b qtmr0_ tmr1 pdb0_extrg 60 46 ptc7 disabled adc0_se2/ cmp2_in2 ptc7 uart0_tx xbar_out2 61 47 ptd0/ llwu_p11 disabled cmp0_in0 ptd0/ llwu_p11 uart0_rx xbar_in2 62 ptj3 disabled ptj3 lpuart0_ rts_b cmp2_out 63 ptj4 disabled ptj4 lpuart0_ cts_b 64 48 ptd1 disabled ptd1 uart1_tx spi0_pcs0 xbar_out3 qtmr0_ tmr3 65 49 ptd2/ llwu_p10 disabled cmp0_in1 ptd2/ llwu_p10 uart1_rx spi0_sck xbar_in3 66 ptj5 disabled ptj5 lpuart0_tx 67 ptj6/ llwu_p18 disabled ptj6/ llwu_p18 lpuart0_rx 68 ptj7 disabled ptj7 69 50 ptd3 disabled ptd3 uart1_cts_ b spi0_mosi 70 ptk0 disabled adc0_se12 ptk0 71 nc nc 72 nc nc 73 nc nc 74 nc nc 75 ptk1 disabled adc0_se13 ptk1 76 51 ptd4/ llwu_p9 disabled adc0_se3 ptd4/ llwu_p9 uart1_rts_ b spi0_miso pinout kinetis km34 sub-family data sheet, rev. 2, may 2015 45 freescale semiconductor, inc. 144 qfp 100 qfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 77 52 ptd5 disabled adc0_se4a ptd5 lptmr0_ alt3 qtmr0_ tmr0 uart3_cts_ b 78 53 ptd6/ llwu_p8 disabled adc0_se5a ptd6/ llwu_p8 lptmr0_ alt2 cmp1_out uart3_rts_ b 79 54 ptd7/ llwu_p7 disabled cmp0_in4 ptd7/ llwu_p7 i2c0_scl xbar_in4 uart3_rx 80 55 pte0 disabled pte0 i2c0_sda xbar_out4 uart3_tx clkout 81 ptk2 disabled adc0_se14 ptk2 uart0_tx 82 ptk3/ llwu_p19 disabled adc0_se15 ptk3/ llwu_p19 uart0_rx 83 56 pte1 reset_b pte1 reset_b 84 57 pte2 extal0 extal0 pte2 ewm_in xbar_in6 i2c1_sda 85 58 pte3 xtal0 xtal0 pte3 ewm_out_b afe_clk i2c1_scl 86 59 vss vss vss 87 60 vssa vssa vssa 88 61 vdda vdda vdda 89 62 vdd vdd vdd 90 63 pte4 disabled pte4 lptmr0_ alt1 uart2_cts_ b ewm_in 91 64 pte5/ llwu_p6 disabled pte5/ llwu_p6 qtmr0_ tmr3 uart2_rts_ b ewm_out_b 92 65 pte6/ llwu_p5 swd_dio cmp0_in2 pte6/ llwu_p5 xbar_in5 uart2_rx i2c0_scl swd_dio 93 66 pte7 swd_clk adc0_se6a pte7 xbar_out5 uart2_tx i2c0_sda swd_clk 94 67 ptf0/ llwu_p4 disabled adc0_se7a/ cmp2_in3 ptf0/ llwu_p4 rtc_clkout qtmr0_ tmr2 cmp0_out 95 68 ptf1 disabled lcd_p0/ adc0_se8/ cmp2_in4 ptf1 qtmr0_ tmr0 xbar_out6 lcd_p0 96 69 ptf2 disabled lcd_p1/ adc0_se9/ cmp2_in5 ptf2 cmp1_out rtc_clkout lcd_p1 97 ptk4 disabled lcd_p51 ptk4 xbar_in9 afe_clk lcd_p51 98 ptk5 disabled ptk5 uart1_rx 99 ptk6 disabled ptk6 uart1_tx 100 70 ptf3/ llwu_p20 disabled lcd_p2 ptf3/ llwu_p20 spi1_pcs0 lptmr0_ alt2 uart0_rx lcd_p2 101 71 ptf4 disabled lcd_p3 ptf4 spi1_sck lptmr0_ alt1 uart0_tx lcd_p3 102 72 ptf5 disabled lcd_p4 ptf5 spi1_miso i2c1_scl lcd_p4 103 73 ptf6/ llwu_p3 disabled lcd_p5 ptf6/ llwu_p3 spi1_mosi i2c1_sda lcd_p5 104 74 ptf7 disabled lcd_p6 ptf7 qtmr0_ tmr2 clkout cmp2_out lcd_p6 pinout 46 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. 144 qfp 100 qfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 105 ptk7 disabled lcd_p52 ptk7 i2c0_scl xbar_out9 lcd_p52 106 ptl0 disabled lcd_p53 ptl0 i2c0_sda lcd_p53 107 nc nc 108 nc nc 109 nc nc 110 75 ptg0 disabled lcd_p7 ptg0 qtmr0_ tmr1 lptmr0_ alt3 lcd_p7 111 76 ptg1/ llwu_p2 disabled lcd_p8/ adc0_se10 ptg1/ llwu_p2 lptmr0_ alt1 lcd_p8 112 77 ptg2/ llwu_p1 disabled lcd_p9/ adc0_se11 ptg2/ llwu_p1 spi0_pcs0 lcd_p9 113 78 ptg3 disabled lcd_p10 ptg3 spi0_sck i2c0_scl lcd_p10 114 79 ptg4 disabled lcd_p11 ptg4 spi0_mosi i2c0_sda lcd_p11 115 80 ptg5 disabled lcd_p12 ptg5 spi0_miso lptmr0_ alt2 lcd_p12 116 81 ptg6/ llwu_p0 disabled lcd_p13 ptg6/ llwu_p0 lptmr0_ alt3 lcd_p13 117 82 ptg7 disabled lcd_p14 ptg7 lcd_p14 118 83 pth0 disabled lcd_p15 pth0 lpuart0_ cts_b lcd_p15 119 84 pth1 disabled lcd_p16 pth1 lpuart0_ rts_b lcd_p16 120 85 pth2 disabled lcd_p17 pth2 lpuart0_rx lcd_p17 121 86 pth3 disabled lcd_p18 pth3 lpuart0_tx lcd_p18 122 87 pth4 disabled lcd_p19 pth4 lcd_p19 123 88 pth5 disabled lcd_p20 pth5 lcd_p20 124 89 pth6 disabled pth6 uart1_cts_ b spi1_pcs0 xbar_in7 125 90 pth7 disabled pth7 uart1_rts_ b spi1_sck xbar_out7 126 91 pti0/ llwu_p21 disabled cmp0_in5 pti0/ llwu_p21 uart1_rx xbar_in8 spi1_miso spi1_mosi 127 92 pti1 (this pin is true open drain pad. external pull- up resistor should be added.) disabled pti1 uart1_tx xbar_out8 spi1_mosi spi1_miso 128 ptl1 disabled lcd_p54 ptl1 xbar_in10 lcd_p54 129 ptl2 disabled lcd_p55 ptl2 xbar_out10 lcd_p55 130 93 pti2/ llwu_p22 disabled lcd_p21 pti2/ llwu_p22 lpuart0_rx lcd_p21 131 94 pti3 disabled lcd_p22 pti3 lpuart0_tx cmp2_out lcd_p22 132 95 vss vss vss pinout kinetis km34 sub-family data sheet, rev. 2, may 2015 47 freescale semiconductor, inc. 144 qfp 100 qfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 133 vdd vdd vdd 134 96 vll3 vll3 vll3 135 97 vll2 vll2 vll2/ lcd_p60 ptm0 lcd_p60 136 98 vll1 vll1 vll1/ lcd_p61 ptm1 lcd_p61 137 99 vcap2 vcap2 vcap2/ lcd_p62 ptm2 lcd_p62 138 100 vcap1 vcap1 vcap1/ lcd_p63 ptm3 lcd_p63 139 ptl3 disabled lcd_p56 ptl3 ewm_in lcd_p56 140 ptl4 disabled lcd_p57 ptl4 ewm_out_b lcd_p57 141 ptl5/ llwu_p23 disabled lcd_p58 ptl5/ llwu_p23 lcd_p58 142 ptl6 disabled lcd_p59 ptl6 lcd_p59 143 pti4 disabled lcd_p44 pti4 lcd_p44 144 nc nc 5.2 km3x_256 family pinouts 5.2.1 100-pin lqfp the following figure represents the km3x_256 100 lqfp pinouts: pinout 48 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. 60 59 58 57 56 55 54 53 52 51 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ptc1 ptc0 ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1/llwu_p17 vss vdd ptb0 pta7 pta6/llwu_p14 pta5 pta4/llwu_p15 pta3 pta2 pta1 pta0/llwu_p16 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 ptg0 ptf7 ptf6/llwu_p3 ptf5 ptf4 ptf3/llwu_p20 ptf2 ptf1 ptf0/llwu_p4 pte7 pte6/llwu_p5 pte5/llwu_p6 pte4 vdd vdda vssa vss pte3 pte2 pte1 pte0 ptd7/llwu_p7 ptd6/llwu_p8 ptd5 ptd4/llwu_p9 25 24 23 22 21 xtal32 vbat ptc4 ptc3/llwu_p13 ptc2 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 99 79 78 77 76 vcap2 ptg4 ptg3 ptg2/llwu_p1 ptg1/llwu_p2 50 49 48 47 46 45 44 43 42 41 ptd3 ptd2/llwu_p10 ptd1 ptd0/llwu_p11 ptc7 ptc6 ptc5/llwu_p12 afe_sdadm3/cmp1_in5 afe_sdadp3/cmp1_in4 vref afe_sdadm2/cmp1_in3 afe_sdadp2/cmp1_in2 vrefl vrefh afe_sdadm1 afe_sdadp1 afe_sdadm0 afe_sdadp0 afe_vssa afe_vdda tamper0 tamper1 tamper2 vss extal32 98 vll1 97 vll2 96 vll3 95 vss 94 pti3 93 pti2/llwu_p22 92 pti1 91 pti0/llwu_p21 90 pth7 89 pth6 88 pth5 80 ptg5 ptg6/llwu_p0 ptg7 81 82 83 pth0 84 pth1 85 pth2 86 pth3 87 pth4 100 vcap1 figure 11. 100-pin lqfp pinout diagram 5.2.2 144-pin lqfp the following figure represents the km3x_256 144 lqfp pinouts: pinout kinetis km34 sub-family data sheet, rev. 2, may 2015 49 freescale semiconductor, inc. 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 75 74 73 60 59 58 57 56 55 54 53 52 51 72 71 70 69 68 67 66 65 64 63 62 61 25 24 23 22 21 40 39 38 37 50 49 48 47 46 45 44 43 42 41 36 35 34 33 32 31 30 29 28 27 26 99 79 78 77 76 98 97 96 95 94 93 92 91 90 89 88 80 81 82 83 84 85 86 87 100 108 nc 107 106 105 104 103 102 101 nc ptl0 ptk7 ptf7 ptf6/llwu_p3 ptf5 ptf4 116 ptg6/llwu_p0 115 114 113 112 111 110 109 ptg5 ptg4 ptg3 ptg2/llwu_p1 ptg1/llwu_p2 ptg0 nc 124 pth6 123 122 121 120 119 118 117 pth5 pth4 pth3 pth2 pth1 pth0 ptg7 132 vss 131 130 129 128 127 126 125 pti3 pti2/llwu_p22 ptl2 ptl1 pti1 pti0/llwu_p21 pth7 140 ptl4 139 138 137 136 135 134 133 ptl3 vcap1 vcap2 vll1 vll2 vll3 vdd 144 143 142 141 nc pti4 ptl6 ptl5/llwu_p23 ptk6 ptd7/llwu_p7 ptd6/llwu_p8 ptd5 ptd4/llwu_p9 ptk5 ptk4 ptf2 ptf1 ptf0/llwu_p4 pte7 pte6/llwu_p5 pte5/llwu_p6 pte4 vdd vdda pte0 ptk2 ptk3/llwu_p19 pte1 pte2 pte3 vss vssa ptf3/llwu_p20 ptk1 nc nc nc nc ptk0 ptd3 ptj7 ptj6/llwu_p18 ptj5 ptd2/llwu_p10 ptd1 ptj4 ptj3 ptd0/llwu_p11 ptc7 ptc6 ptc5/llwu_p12 nc nc afe_sdadm3/cmp1_in5 afe_sdadp3/cmp1_in4 vref afe_sdadm2/cmp1_in3 afe_sdadp2/cmp1_in2 vrefl vrefh afe_sdadm1 afe_sdadp1 afe_sdadm0 afe_sdadp0 afe_vssa afe_vdda tamper0 tamper1 tamper2 vss nc nc ptb1/llwu_p17 vss vdd ptj2 ptb0 ptj1 ptj0 pta7 pta6/llwu_p14 pta5 pta4/llwu_p15 pta3 pta2 pti7 pti6 pta1 pta0/llwu_p16 pti5 nc nc ptb6 ptb5 ptb4 ptb3 ptb2 nc nc extal32 xtal32 vbat ptc4 ptc3/llwu_p13 ptc2 ptc1 ptc0 ptb7 figure 12. 144-pin lqfp pinout diagram 6 ordering parts ordering parts 50 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. 6.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: ? MKM34Z256VLL7 ? mkm34z256vlq7 7 part identification 7.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 7.2 format part numbers for this device have the following format: q km## a fff r t pp cc n 7.3 fields following table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status ? m = fully qualified, general market flow ? p = pre-qualification km## kinetis family ? km34 a key attribute ? z = cortex ? -m0+ fff program flash memory size ? 256 = 256 kb r silicon revision ? (blank) = main ? a = revision after main t temperature range (c) ? v = C40 to 105 pp package identifier ? ll = 100 lqfp (14 mm x 14 mm) ? lq = 144 lqfp (20 mm 20 mm) table continues on the next page... part identification kinetis km34 sub-family data sheet, rev. 2, may 2015 51 freescale semiconductor, inc. field description values cc maximum cpu frequency (mhz) ? 7 = 75 mhz n packaging type ? r = tape and reel ? (blank) = trays 7.4 example this is an example part number: ? MKM34Z256VLL7 8 terminology and guidelines 8.1 definition: operating requirement an operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 8.1.1 example this is an example of an operating requirement: symbol description min. max. unit v dd 1.0 v core supply voltage 0.9 1.1 v 8.2 definition: operating behavior unless otherwise specified, an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. terminology and guidelines 52 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. 8.2.1 example this is an example of an operating behavior: symbol description min. max. unit i wp digital i/o weak pullup/ pulldown current 10 130 a 8.3 definition: attribute an attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 8.3.1 example this is an example of an attribute: symbol description min. max. unit cin_d input capacitance: digital pins 7 pf 8.4 definition: rating a rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: ? operating ratings apply during operation of the chip. ? handling ratings apply when the chip is not powered. 8.4.1 example this is an example of an operating rating: symbol description min. max. unit v dd 1.0 v core supply voltage C0.3 1.2 v terminology and guidelines kinetis km34 sub-family data sheet, rev. 2, may 2015 53 freescale semiconductor, inc. 8.5 result of exceeding a rating 40 30 20 10 0 measured characteristic operating rating failures in time (ppm) the likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 8.6 relationship between ratings and operating requirements C - no permanent failure - correct operation normal operating range fatal range expected permanent failure fatal range expected permanent failure operating rating (max.) operating requirement (max.) operating requirement (min.) operating rating (min.) operating (power on) degraded operating range degraded operating range C no permanent failure handling range fatal range expected permanent failure fatal range expected permanent failure handling rating (max.) handling rating (min.) handling (power off) - no permanent failure - possible decreased life - possible incorrect operation - no permanent failure - possible decreased life - possible incorrect operation 8.7 guidelines for ratings and operating requirements follow these guidelines for ratings and operating requirements: ? never exceed any of the chips ratings. terminology and guidelines 54 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. ? during normal operation, dont exceed any of the chips operating requirements. ? if you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 8.8 definition: typical value a typical value is a specified value for a technical characteristic that: ? lies within the range of values specified by the operating behavior ? given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions typical values are provided as design guidelines and are neither tested nor guaranteed. 8.8.1 example 1 this is an example of an operating behavior that includes a typical value: symbol description min. typ. max. unit i wp digital i/o weak pullup/pulldown current 10 70 130 a 8.8.2 example 2 this is an example of a chart that shows typical values for various voltage and temperature conditions: terminology and guidelines kinetis km34 sub-family data sheet, rev. 2, may 2015 55 freescale semiconductor, inc. 0.90 0.95 1.00 1.05 1.10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 c 105 c 25 c C40 c v dd (v) i (a) dd_stop t j 8.9 typical value conditions typical values assume you meet the following conditions (or other conditions as specified): symbol description value unit t a ambient temperature 25 c v dd 3.3 v supply voltage 3.3 v 9 revision history the following table provides a revision history for this document. table 40. revision history rev. no. date substantial changes 2 05/2015 initial public release revision history 56 kinetis km34 sub-family data sheet, rev. 2, may 2015 freescale semiconductor, inc. how to reach us: home page: freescale.com web support: freescale.com/support information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters that may be provided in freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including typicals, must be validated for each customer application by customer's technical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: www.freescale.com/salestermsandconditions . freescale, the freescale logo, and kinetis are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. all other product or service names are the property of their respective owners. arm and cortex are registered trademarks of arm limited (or its subsidiaries) in the eu and/or elsewhere. all rights reserved. ? 2014-2015 freescale semiconductor, inc. document number km34p144m75sf0 revision 2, may 2015 |
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